A polymer based Ferroelectric gate FET at IT nonvolatile memory on bulk silicon is demonstrated. Spin-coated 40nm and lOOnm P(VDF-TrFE) (70%-30%) ultra-thin films have been integrated onto lOnm Si02 layer as gate dielectric into a conventional silicon n-MOSFETs. A IT non-volatile memory cell with an operating voltage as low as 6V, for the thinnest (40nm) gate ferroelectric copolymer dielectric, is demonstrated for the first time. The reported Fe-FET devices have Ion/Ioff ranging from 105 to 10 6 and retention time up to few days. Experiments show reliable memory operation up to 105 cycles and programming time in the order of ms.© 2008 IEEE.
Low voltage ferroelectric FET with sub-l00nm copolymer P(VDF-TrFE) gate dielectric for non-volatile IT memory
Salvatore G. A.;
2008-01-01
Abstract
A polymer based Ferroelectric gate FET at IT nonvolatile memory on bulk silicon is demonstrated. Spin-coated 40nm and lOOnm P(VDF-TrFE) (70%-30%) ultra-thin films have been integrated onto lOnm Si02 layer as gate dielectric into a conventional silicon n-MOSFETs. A IT non-volatile memory cell with an operating voltage as low as 6V, for the thinnest (40nm) gate ferroelectric copolymer dielectric, is demonstrated for the first time. The reported Fe-FET devices have Ion/Ioff ranging from 105 to 10 6 and retention time up to few days. Experiments show reliable memory operation up to 105 cycles and programming time in the order of ms.© 2008 IEEE.I documenti in ARCA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.