An 8-channel DRAGO readout circuit for silicon detectors with integrated front-end JFET

We have developed a CMOS circuit to be used with Silicon Drift Detectors (SDDs) for X-ray spectroscopy and γ-ray imaging applications. The circuit operates with the input transistor integrated directly on the detector wafer. The circuit is composed of 8 analog channels, each including a low-noise voltage preamplifier, a 6th order semi-Gaussian shaping amplifier, with four selectable peaking times from 1.8 μs up to 6 μs, and a peak stretcher. The integrated time constant used for the shaping are implemented by means of a recently proposed 'RC' cell. This cell is based on the de-magnification of the current flowing in a resistor R thanks to the use of current mirrors. The 8 analog channels of the chip are multiplexed to a single analog output. A digital section provides self-resetting of the channels, trigger output and the external programming of independent threshold on the analog channels by means of a 3 bit DAC and a programmable serial register. In this work, the main features of the circuit are described. The measurement results obtained in the characterization of the prototype are then reported and discussed. The energy resolution measured using a single channel of the chip with a Silicon Drift Detector Droplet (SDD 3) is of 128 eV at 6 keV with the detector cooled at -20°C. Spectroscopy measurements using a multi-element SDD are also shown. © 2006 IEEE.